Introduction
- Interrupts are crucial for managing asynchronous events and ensuring efficient CPU utilization.
- Understanding the different types of interrupts and their handling mechanisms is fundamental for system programming, operating system design, and hardware interfacing.
Definition
- An interrupt is an exceptional event that causes the CPU to temporarily transfer its processing control from the currently executing program to a different program that provides service to the exceptional event.
- An interrupt is the interruption of the execution of an ongoing user program. The execution of the user program resumes as soon as the interrupt processing is completed.
- An interrupt is a process of creating a temporary halt/pause of a currently executing program and allows peripheral devices to access the microprocessor.
- Interrupts are signals that indicate the need for immediate attention from the CPU. They temporarily halt the current CPU operations, save the state of the current processes, and execute a specific piece of code known as an interrupt handler or interrupt service routine (ISR). Once the ISR has been executed, the CPU resumes its previous operations.
Features
- Interrupts are essential for handling asynchronous events, and improving the efficiency and responsiveness of computer systems.
- An interrupt is also acknowledged by the CPU when it has completed the currently executing instruction normally.
- The occurrence of Interrupt is known by the CPU using the status of the Interrupt flag register.
- The interrupt is performed by the processor and the operating system, which in turn are also responsible for suspending the execution of the user program, and later after interrupt handling, resumes the user program from the point of interruption.
- There are more than 256 software and hardware interrupts in the 8086 microprocessor.
Interrupt Working Mechanism (Interrupts Handling)
- On the occurrence of an interrupt, an interrupt request (in the form of a signal) is issued to the CPU/Processor. The CPU on receipt of an interrupt request suspends the operation of the currently executing program, saves the context of the currently executing program, and starts executing the program which services that interrupt request. This program is also known as an interrupt handler. After the interrupting condition/device has been serviced the execution of the original program is resumed.
- In other words, once a CPU knows that an interrupt has occurred then –
- The CPU must find out the source of the interrupt and check why the interrupt has occurred including not only the device but also why that device has raised the interrupt. Once the interrupt condition is determined the necessary program called ISRs (Interrupt servicing routines) must be executed such that the CPU can resume further operations. Thus, on occurrence of an Interrupt the related ISR is executed by the CPU.
- The CPU then acquires the address of the interrupt service routine, which is stored in the memory (in general).
- When an Interrupt occurs then the program, the CPU executes before the interrupt is interrupted/suspended till the CPU executes the Interrupt service program and the context of this program is to be saved in the memory. It is the operating system that before an interrupt service routine is executed the previous content of the CPU registers should be stored, such that the execution of an interrupted program can be restarted without any change from the point of interruption. Therefore, at the beginning of interrupt processing the essential context of the processor is saved either into a special save area in main memory or into a stack. This context is restored when the interrupted service routine is finished, thus, the interrupted program execution can be restarted from the point of interruption.
- Finally, the CPU executes the interrupt service routine till the completion of the routine. A RETURN statement marks the end of this routine. After that, the control is passed back to the interrupted(previous) program.
- Interrupt Servicing Routines(ISR) :
- The ISRs are pre-defined programs written for specific interrupt conditions.
- The microprocessor responds to arising interrupts with an ISR, which is a short program or subroutine to instruct the microprocessor, on how to handle the arised interrupt.
- Interrupt Vectors Table(IVT) :
- IVT is also known as the Interrupt Pointers Table.
- An interrupt vector table (IVT) is a data structure that associates each interrupt with its corresponding ISR. The table contains pointers to the ISRs for each interrupt type. When an interrupt occurs, the CPU uses the interrupt number to index into the IVT and fetch the address of the ISR to execute.
- IVT is a 1KB memory size table that contains the list of more than 256 interrupt index addresses as pointers numbered from 0 to 255. The number assigned to an interrupt pointer is known as the type of that interrupt. For example, Type 0, Type 1, Type 2,………..Type 255 interrupt.
- Interrupt when occurs, is handled and operated successfully through the Interrupt cycle. In the interrupt cycle, the responsibility of the CPU/Processor is to check whether any interrupts have occurred checking the presence of the interrupt signal. In case, no interrupt needs service, the processor proceeds to the next instruction of the current program. In case an interrupt needs servicing then the interrupt is processed the following way –
- Suspend the execution of the current program and save its context.
- Set the Program counter to the starting address of the interrupt service routine of the interrupt acknowledged.
- The processor then executes the instructions in the interrupt-servicing program. The interrupt servicing programs are normally part of the operating system.
- After completing the interrupt servicing program the CPU can resume the previous program it has suspended.
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Briefly, when an interrupt occurs, the following steps are typically taken:-
- Save Context: The CPU saves the state of the current process, including the program counter and registers.
- Identify Interrupt: The CPU determines the source of the interrupt.
- Execute ISR: The appropriate interrupt service routine is executed to handle the interrupt.
- Restore Context: The CPU restores the saved state and resumes the interrupted process.
Reason of Interrupts
- An interrupt may be generated by several sources, which may be either internal or external to the CPU.
- Some common factors that influence interruption are –
Interrupt are generated by executing the program itself (called traps) |
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Interrupt generated by clock (pulse) in the processor | Generally used on the expiry of time allocated for a program, in multiprogramming operating systems. |
Interrupts generated by I/O devices and their interfaces |
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Interrupts on Hardware failure |
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Advantages of Interrupts
- They enable the CPU to respond quickly to urgent tasks, such as handling input/output operations, system calls, and error conditions. Thus, it increases the processing efficiency of the CPU.
- It decreases the waiting time of a process.
Types of Interrupts
- Interrupts can be broadly categorized based on their source and how they are generated. They are –
(I) Hardware Interrupt
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- This type of interrupt signal is generated by hardware or peripheral devices (e.g., keyboard, mouse, disk drives).
- Hardware Interrupt is further divided into:
- Maskable Interrupts (IRQ):
- These can be enabled or disabled by the CPU using an interrupt mask.
- They have lower priority compared to non-maskable interrupts.
- Example: Interrupt Request (IRQ) lines in the x86 architecture.
- Non-Maskable Interrupts (NMI):
- These cannot be disabled by the CPU and are used for high-priority and critical events.
- Interrupt generated by severe errors (aborts) from which recovery is not possible (e.g., hardware failures).
- Timer Interrupt – Generated by the system timer at regular intervals which is used for task scheduling, timekeeping, and preemptive multitasking.
- Keyboard Interrupt – When a key is pressed, the keyboard controller sends an interrupt signal to the CPU. The CPU stops its current tasks and executes the keyboard ISR to process the key press.
- Example: Power failure, hardware failure.
- Maskable Interrupts (IRQ):
(ii) Software Interrupt
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- The software interrupts occur by executing a dedicated instruction/program code segment/by internal abnormal conditions such as overflow; division by zero etc.
- The software interrupts are further divided into:-
- System Calls (Traps):
- A user program requests a system service, such as file operations, by invoking a software interrupt. It is used by programs to request services from the operating system.
- Breakpoint Interrupt – Used by debuggers to halt program execution at specific points. For example – Setting a breakpoint in a debugger during program testing.
- Example: Interrupt 0x80 in Linux for system calls.
- Exceptions:
- It is generated by the CPU itself to handle errors or specific conditions when it detects a particular condition during program execution.
- Interrupt generated by page faults conditions that can be corrected and the program can be restarted (e.g., page faults).
- Example: Divide-by-zero error, invalid opcode.
- System Calls (Traps):
- A programmer can also create an interrupt as per the requirement of the program for the microprocessor by inserting INT instruction at the desired point in the program while debugging a program.
- (iii) Internal Interrupt/Exceptions
- Examples of software interrupts are:
- TYPE 0 : division by zero.
- TYPE 1 : single-step execution for debugging a program.
- TYPE 2 : power failure condition.
- TYPE 3 : breakpoint interrupt.
- TYPE 4 : overflow interrupt.
- Examples of software interrupts are:
Use/Application of Interrupts
- Interrupts are a useful mechanism because it improves the efficiency of processing.
- As we know almost all the external devices are comparatively slower than the processor, therefore, in a typical system, a processor has to continually test whether an input value has arrived or a printout has been completed, in turn wasting a lot of CPU time.
- With the interrupt facility, the CPU is freed from the task of testing the status of Input/Output devices and can do useful other processing during this time, thus increasing the processing efficiency.
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