Instruction Cycle

Introduction

• • The instruction cycle is the basic operational process of a computer system.
  • It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction describes, and then carries out those actions. This cycle is repeated continuously by a computer’s central processing unit (CPU), from boot-up until the computer has shut down. During instruction cycle, a group of wires carries information between different components is called bus.
  • T-state is defined as one subdivision of operation performed in one clock period. These subdivisions are internal states synchronized with the system clock, and each T-state is precisely equal to one clock period.

Definition

• Instruction cycle is a type of processing cycle in which a program is processed in a series of sub-cycles of an instruction cycle(such as fetch, indirect, execute, and interrupt cycles) sequentially.

Features

• Instruction cycle is also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle.
• Normally, the instruction cycle is executed sequentially i.e., each instruction being processed before the next one is started. But, in most modern CPUs, the instruction cycles are executed concurrently, and often in parallel, through an instruction pipelining.
• An Instruction cycle is coded in a 2-bit form is called instruction cycle code (ICC). The ICC can represent the state of the processor in terms of cycle. For example, we can use:
  00 for Fetch cycle
  01 for Indirect cycle
  10 for Execute cycle
  11 for Interrupt cycle

At the end of each of the four sub-cycles, the ICC is set appropriately.

Types of Instruction Cycle

• A program execution occurs as a series of sequence of instruction cycles. Each instruction cycle is made up of a number of sub cycles(which includes fetch, indirect, execute, and interrupt cycles), with only fetch and execute cycles always occurring. Each sub cycle involves one or more micro-operations as per program structure. The sub cycle of Instruction cycle in sequence for a given machine consists of four sub-cycles are – 

(A)The Fetch Cycle

• The beginning of each instruction cycle is the fetch cycle, and causes an instruction to be fetched from memory.
• The fetch cycle consists of four micro-operations that are executed in three timing steps. The fetch cycle can be written as:
  T1 : MAR ← PC
  T2 : MBR ← [MAR]
         PC ← PC + IL
  T3 : IR ← MBR
  (where MAR, PC, MBR and IR are the basic CPU registers. IL is the instruction length. Here, a clock is available for timing purposes and that it emits regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all the units are of equal duration. Each micro-operation can be performed within the time of a single time unit. The notation (T1, T2, T3) represents successive time units.)
  • In the first step or time unit (T1), the content of PC is moved to MAR.
  • In the second step or time unit (T2), the contents of memory location specified by MAR is moved to MBR and the contents of the PC is incremented by IL times.
  • In the third step or time unit (T3) the content of MBR is moved to IR.

(B)The Indirect Cycle

• It is the second step of Instruction cycle.
• Once an instruction is fetched from fetch cycle, the next step is to fetch the operands which is done by the Indirect cycle.
• As we know that, the instruction may have direct and indirect addressing modes. An indirect address of an operand is handled using indirect cycle.
• The steps of micro-operations during the indirect cycle are:-
  T1 : MAR ← IR (address)
  T2 : MBR ← [MAR]
  T3 : IR (address) ← MBR (address)

In this micro-operation, the MAR is loaded with the address field of IR register (received from fetch cycle). Now the operand value from MAR address is transferred into MBR. Then the memory is read to fetch the address of operand, which is transferred to the address field of IR through MBR as data is received in MBR during the read operation.
Thus, the IR now is in the same state as of direct address, viz., as if indirect addressing had not been used. IR is now ready for the execute cycle.

(C)The Execute Cycle

• The fetch and indirect cycles involve a small, fixed sequence of micro-operations.
• The fetch and indirect cycles has fixed sequence of micro-operations that are common to all instructions.
• The execute cycle steps of micro-operations are different for all instructions in addition the addressing mode may be different. All such information generally is dependent on the opcode of the instruction Register (IR). Thus, IR input to Address Register for Control Memory is desirable. Thus, there exist a decoder from IR to Address Register for control memory. This decoder translates the opcode of the IR into a control memory address.
• The execute cycle is not fixed sequence of micro-operations(as in fetch and indirect) rather it is variable i.e. for a machine with N different opcodes, there are N different sequences of micro-operations that can occur.
• For example – To explain execute cycle, we take an example i.e. as we know that an add instruction that adds the contents of memory location X to Register R1 with R1 storing the result:
  ADD R1, X
  To do this, the sequence of micro-operations may be: –
  T1 : MAR ← IR (address)
  T2 : MBR ← [MAR]
  T3 : R1 ← R1 + MBR
  In execute cycle IR contains the ADD instruction and its direct operand address (memory location X). At time T1, the address portion of the IR is transferred to the MAR. At time T2 the referenced memory location is read into MBR Finally, at time T3 the contents of R1 and MBR are added by the ALU.
  In another example :-
  say ISZ X, it increments the content of memory location X by 1. If the result is 0, the next instruction in the sequence is skipped. The sequence of micro-operations for this instruction example are:
  T1 : MAR ← IR (address)
  T2 : MBR ← [MAR]
  T3 : MBR ← MBR+ 1
  T4 : [MAR] ← MBR
  If (MBR = 0) then (PC ← PC+ I )
  
  NB : Here, this machine we have assumed that MBR can be incremented by ALU directly. The PC register is incremented if MBR contains 0. This test and action can be implemented as one micro-operation. Note also that this micro-operation can be performed during the same time unit during which the updated value in MBR is stored back to memory. Such instructions are useful in implementing looping.

(D)The Interrupt Cycle

• On completion of the execute cycle the current instruction execution gets completed.
• At this point, a test is made to determine whether any enabled interrupts have occurred. If so, the interrupt cycle is performed. This cycle does not execute an interrupt but causes start of execution of Interrupt Service Program (ISR). The ISR is executed as just another program instruction cycle. The nature of this cycle varies greatly from one machine to another.
• A typical sequence of micro-operations of the interrupt cycle are:
  T1 : MBR ← PC
  T2 : MAR ← Save-Address
  PC ← ISR- Address
  T3 : [MAR] ← MBR
  Here, at time T1, the contents of the PC are transferred to the MBR, so that they can be saved for return from the interrupt. At time T2, the MAR is loaded with the address at which the contents of the PC are to be saved, and PC is loaded with the address of the start of the interrupt-servicing routine. At time T3, MBR which contains the old value of the PC, is stored in the memory. The processor is now ready to begin the next instruction cycle.